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cyii4sm1300aa ibis4-1300 1.3 mpxl rolling shutter cmos image sensor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05707 rev. *c revised september 21, 2009 overview the ibis4-1300 is a digital cmos active pixel image sensor with sxga format. due to a patented pixel configur ation a 60% fill factor and 50% quantum efficiency are obtained. this is combined with an on-chip double sampling technique to cancel fixed pattern noise. features sxga resolution: 1280 x 1024 pixels high sensitivity 20 v/e - high fill factor 60% quantum efficiency > 50% between 500 and 700 nm. 20 noise electrons = 50 noise photons dynamic range: 69 db (2750:1) in single slope operation extended dynamic range mode (80?100 db) in double slope integration on-chip 10 bit, 10 mega samples/s adc programmable gain and offset output amplifier 4:1 sub sampling viewfinder mode (320x256 pixels) electronic shutter 7 x 7 m 2 pixels low fixed pattern noise (1% vsat p/p) low dark current: 344 pa/cm 2 (1055 electrons/s, 1 minute auto saturation) rgb or monochrome digital (adc) gamma correction ordering information marketing part number description package CYII4SM1300AA-QDC mono with glass 84-pin lcc cyii4sm1300aa-qwc mono without glass cyii4sd1300aa-qdc color diagonal with glass [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 2 of 35 architecture of image sensor block diagram the ibis4-1300 is an sxga cmos image sensor. the chip is comp osed of 3 modules: an image sensor core, a programmable gain output amplifier, and an on-chip 10 bit adc. figure 1. shows the architecture of the image sensor core. figure 1. architecture of image sensor core 1280 x 1024 pixel array 10 bit adc output amplifier pixel array 1286 x 1030 pixels readout row pointer reset row pointer y readout shift register y reset shift register column amplifiers x shift register clock_yl clock_yr clock_x sync_x sync_yl sync_yr [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 3 of 35 image sensor core ? focal plane array the core of the sensor is the pixel array with 1280 x 1024 (sxga) active pixels. the name 'active pi xels' refers to the amplifying element in each pixel. this type of pixels offer a high light sensitivity combined with low temporal noise. the actual array size is 1286 x 1030 including the 6 dummy pixels in x and y. although the dummy pixels fall outside the sxga format, their information can be used e.g. for color filter array interpolation. figure 2. pixel selection ? principle next to the pixel array there are two y shift registers, and one x shift register with the column am plifiers. the shift registers act as pointers to a certain row or column. the y readout shift register accesses the row (line) of pixels that is current ly readout. the x shift register selects a particular pixel of this row. the second y shift register is used to point at the row of pixels that is reset. the delay between both y row pointers determines the integration time -thus realizing the electronic shutter. a clock and a synchronization pulse control the shift registers. on every clock pulse, the pointer shifts one row/column further. a sync pulse is used to reset and initialize the shift registers to their first position. the smart column amplifiers compensate the offset variations between individual pixels. to do so, they need a specific pulse pattern on specific control signals before the start of the row readout. ta b l e 1 . summarizes the optical and electrical characteristics of the image sensor. some specifications are influenced by the output amplifier gain setting (e .g., temporal noise, conversion factor,...). therefore, all specifications are referred to an output amplifier gain equal to 1. y readout shift register xshiftregister table 1. optical and electrical characteristics pixel characteristics pixel structure 3-trans istor active pixel photodiode high fill factor photodiode pixel size 7 x 7 m 2 resolution 1286 x 1030 pixels sxga plus 6 dummy rows and columns pixel rate with on-chip adc nominal 10 mhz (note 1) (note 2) frame rate with on-chip adc about 7 full frames/s at nominal speed frame rate with analog output up to 23 full frames per second (see table1.1) [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 4 of 35 table 1.1. in this table you find achievable values using the analog output. note 1. the pixel rate can be boosted to 37.5 mhz. this requires a few measures. ? increase the analog bandwidth by halving the resistor on pin nbias_oamp ? increase the adc speed by the resistors related to the adc speed (nbiasana1, nbiasana2, pbiasencload) ? experimentally fine tune the relative occurrence of the adc clock relative to the x-pixel clock. note 2. the pure digital scan speed in x and y direction is roughly 50 mhz. this is maximum speed for skipping rows and columns. light sensitivity and detection spectral sensitivity range 400 - 1000 nm spectral response * fill factor 0.165 a/w at 700 nm quantum efficiency * fill factor > 30% between 500 and 700 nm fill factor 60% charge-to-voltage conversion gain 20 v/e - output signal amplitude 1.2 v full well charge [electrons] ibis4-1300: about 90000 saturation, 50000 linear range noise equivalent flux at focal plane (700 nm) 1.1e-4 lx*s (at focal plane) 6.3 e-7 s.w/m2 sensitivity 7 v/lx.s 1260 v.m2/w.s mtf at nyquist frequency 0.4-0.5 at 450 nm 0.25-0.35 at 650 nm optical cross talk 10% to 1 st neighbor 2% to 2 nd neighbor image quality temporal noise (dark, short integration time ) 20 noise electrons = 50 peak noise photons 3 400 v rms dynamic range (analog output, before adc conversion) 2750:1 69 db dark current 344 pa/cm 2 at 21oc 19 mv/s 1055 electrons/s dark current non-uniformity typically 15% rms of dark current level. fixed pattern noise (dark, short integration time) 9.6 mv peak-to-peak 1-2 mv rms photo-response non-uniformity (prnu) 10% peak-to-peak at ? of saturation signal yield criteria no missing columns nor rows less than 100 missing pixels, clusters=<4 pixels table 1. optical and electrical characteristics (continued) pixel characteristics xpixels ypixels x freq x clock x blanking line time frame time frame rate pixel rate pixel rate freq # # hz sec sec sec sec per sec sec hz 1286 1030 1,00e+07 1,00e-07 6,25e-06 0,00013 4850 0,138895500 7,20 1,049e-07 9536522 1286 1030 2,00e+07 5,00e-08 6,25e-06 0,00007 0550 0,072666500 13,76 5,486e-08 18228207 1286 1030 3,00e+07 3,33e-08 6,25e-06 0,00004 9117 0,050590167 19,77 3,819e-08 26182559 1286 1030 3,75e+07 2,67e-08 6,25e-06 0,000040543 0,041759633 23,95 3,153e-08 31719148 1286 512 3,75e+07 2,67e-08 6,25e-06 0,00004 0543 0,020758187 48,17 3,153e-08 31719148 [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 5 of 35 light sensitivity figure 3. spectral response * fill factor of ibis4-1300 pixels anti-blooming overexposure suppression > 105 smear absent features and general specifications electronic shutter rolling curtain type increment = line time = 135 s viewfinder mode 4 x sub-sampling (320 x 256 pixels) digital output 10 bit color filter arra y primary colors (red, green, blue) rgb diagonal stripe pattern or bayer pattern die size 10.30 x 9.30 mm 2 package 84 pins lcc chip carrier 0.460 inch cavity supply voltage 5 v stabilized (e.g. from a 7805 regulator) power supply feed trough (dvout/dvdd) < 0.3 for low-frequencies (< 1 mhz) < 0.05 for high frequencies (> 1 mhz) power dissipation (continuous operation, 10 mhz, adc outputs loaded) min. 50 ma, typ. 70 ma, max. 90 ma table 1. optical and electrical characteristics (continued) pixel characteristics note 3. peak noise photons are defined as (noise electrons) / (ff*peak qe). 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 400 500 600 700 800 900 1000 wavelength [nm] response [a/w] 10% 20% 30% 40% [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 6 of 35 figure 3. shows the spectral response characteristic. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g., interconnection lines. the sensor is light sensitive bet ween 400 and 1000 nm. the peak qe * ff is more than 30% between 500 and 700 nm. in view of a fill factor of 60%, the qe is thus larger than 50% between 500 and 700 nm. figure 4. near infrared spectral response ibis4 near-ir spectral response 1.00e-03 1.00e-02 1.00e-01 1.00e+00 800 850 900 950 1000 1050 1100 wavelength [nm] spectral response (* ff) [a/w] 10% qe 50% qe plain diode pixel array 1% qe calculationofsensitivityin[v/lx.s] pixel area a 49 e-12 m2 fill factor ff 60% spectral response sr 0.22 a/w (average) ff*sr 0.13 a/w (average over wavelength) pixel capacitance ceff 5e-15 f sensitivity = ff*sr*ceff/a 1.27e+3 [v.w/s.m2] conversion to lux: 1w/m2 = about 180 lux, visible light only about 70 lux, including near infrared sensitivity in lux units: 7.08 [v/lx.s] visible light only 18 [v/lx.s] if near ir included [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 7 of 35 color sensitivity charge conversion ? conversion of electrons in an output signal figure 5. ibis4-1300 response curve ? two pixels ? lowest gain setting (0000) 0.00e+00 2.00e+04 4.00e+04 6.00e+04 8.00e+04 1.00e+05 1.20e+05 1.40e+05 1.60e+05 1.80e+05 2.00e+05 400 500 600 700 800 900 1000 wavelength [nm] ibis4b b&w curve: glass window rgb curves: bg39 ir cut off 0 0,2 0,4 0,6 0,8 1 1,2 0 20000 40000 60000 80000 100000 # electrons output signal [v] [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 8 of 35 figure 5. shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. this curve was measured with light of 600 nm, with an integration time of 138.75 ms (10 mhz pixel rate), at minimal gain setting 0000. the resulting voltage/electron curve is independent of these parameters. the conversion gain is 18 v/electron for this gain setting. note that the upper part of the curve (near saturation) is actually a logarithmic response, similar to the fuga1000 sensor. the level of saturation can be adjusted by the voltage on gnd-ab. however, note also that this logarithmic part of the response is not fpn corrected by the on-chip offset correction circuitry. the signal swing (and thus th e dynamic range) is extended by increasing the vdd_reset (pins 59/79) to 5.5v. this is mode of operation is not further documented. ta b l e 2 . shows the pins of the ic that are related to the image sensor core, describing their functionality. table 2. pins of the image sensor core digital controls sync_yr\ 5 reset right y shift re gister (low active, 0 = sync) clk_yr 6 clock right y shift register (shifts on falling edge) eos_yr\ 7 (output) low 1st clk_yr pulse after last row (low active) sync_x\ 28 reset x shift regist er (low active, 0 = sync) clk_x 29 clock x shift register (shifts on falling edge) eos_x\ 8 (output) low 1st clk_x pulse afte r last active column (low active) sync_yl\ 36 reset left y shift register (low active, 0 = sync) clk_yl 37 clock left y shift register (shifts on falling edge) eos_yl\ 38 low 1st clk_yl pulse after last row shy 30 parallel y track & hold (1 = hold, 0 = track) apply pulse pattern - see sensor timing diagram sin 35 column amplifier calibration pulse 1 = calibrate - see sensor timing diagram select 40 selects row indicated by left/right shift register high active (1= select row) apply 5 v dc for normal operation reset 41 resets row indi cated by left/right shift regi ster high active (1 = reset) apply pulse pattern - see timing diagram l/r\ 80 use left or right r egister for select and reset 1 = left / 0 = right - see sensor timing subsmpl 84 activate viewfinder mode (1:4 sub sampling = 320 x 256 pixels) high active, 1 = sub sampling reference voltages dccon 31 control voltage for the dcref voltage generation connect to ground by default dcref 32 reference voltage (output), to be decoupled to gnd should be about 1.2v, can be adjusted by dccon nbiasarray 1 1 megaohm to vdd and decouple to ground by 100 nf capacitor pbias2 2 1 megaohm to ground and decouple to vdd by 100 nf capacitor pbias 3 1 megaohm to ground and decouple to vdd by 100 nf capacitor xmux_nbias 4 100k to vdd and decouple to ground by 100 nf capacitor gnd_ab 54 anti-blooming drain control voltage default: connect to ground. the anti blooming is operational but not maximal. apply about 1 v dc for improved anti-blooming [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 9 of 35 output amplifier the output amplifier stage is user-programmable for gain and offset level. gain and offset are controlled by 4-bit wide words. gain settings are on an exponential scale. offset is controlled by a 4- bit wide dac, which selects the offset voltage between 2 refe rence voltages (vhigh_dac and vlow_dac) on a linear scale. the offset setting is independent of the gain setting. the gain setting is independent of amplifier bandwidth. the amplifier is designed to match the specif ications like the output of the imager arra y. this signal has a data rate of 10 mh z and is located between 1.2 and 2.4v. table 3. summarizes the specifications of the amplifier. the range of the output stage input is between 1 and 4v. a lowest gain the sensor outputs a signal in between 1.2 and 2.2v, whi ch fits into the input range of the amplifie r. the range of the output signal is betwe en 1 and 4.5v, dependent on the gain and off set settings of the amplifier. this range should fit to the input range of th e adc, external or internal. the on-chip adc range is between 2 and 4v. a minimal gain setting of "3" seems necessary for the inter nal adc, and the offset voltage should be set to the low-refere nce voltage of the adc. power and ground vdd_resetl 59 power supply for left reset line driver s apply 5 v dc (default) or about 4?4.5 v for dual slope mode vdd_resetr 79 power supply for right (default) reset line drivers 5 v dc vdd_array 55 power supply for the pixel array 5 v dc vdd 11 34 53 77 power supply of image sensor core & output amplifier 5 v dc gnd 10 33 52 78 ground of image sensor core & output amplifier table 3. summary of output amplifier specifications min. typ max gain 1.2 (gain setting 0) 2.7 (setting 4) 16 (setting 15) output signal range 1 v 4.5 v bandwidth (40 pf load) 12 mhz (gain setting 15) 22 mhz (gain setting 0...8) 33 mhz (gain setting 0) output slew rate (40 pf load) 40 v/ s 50 v/ s80 v/ s table 2. pins of the image sensor core (continued) digital controls [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 10 of 35 figure 6. output amplifier architecture figure 6. shows the architecture of t he output amplifier. first of all, there is a multiplexer whic h selects either the imager core signal or an external pin extin as the input of the amplifier. extin can be used for evaluation, or to feed alternative data to the output. sel_extin controls this switch. then, the signal is fed to the first amplifier stage. this stage has an adjustable gain, controlled by a 4-bit word ('gc_bit0...3'). then, the upper level of the signal must be clipped in some situa- tions (clipping sometimes is necessary when the imager signal is highly saturated, which affects the calibration level. this is visible as black banding at the right side of bright objects in the scene). in order to do this, a voltage should be applied to the 'clip' pin. the signal is clipped if it is higher than vclip - vth,pmos, where vth,pmos is t he pmos threshold voltage and is typically -1 v. if clipping is not necessary, 5 v should be applied to 'clip'. after this, the offset level is added. this offset level is set by a dac, controlled by a 4-bit word (dac_bit0...3). the offset level can be calibrated in two modes: fast offset adjustment or slow offset adjustment. this is controll ed by 'calib_s' and 'calib_f'. the slow adjustment yields a somewhat cleaner image. after this, the signal is buffer ed by a unity feedback amplifier and it leaves the chip. this 2nd amplifier stage determines the maximal readout speed, i.e., the bandwidth and the slew rate of the output signal. the whole amplifier chain is designed for a data rate of 10 mpix/s (at 40 pf). (it is up to the experimenter to increase this speed by reducing the various setting resistors) ta b l e 4 . shows the ibis4-1300 pins used by the output amplifier with a short functional description. power and ground lines are shared between the output ampl ifier and the image sensor. output amplifier offs et level adjustment the purpose of this adjustment is to bring the pixel voltage range as good as possible within the adc range. the offset level of the output signal is controlled by a 4-bit resistive dac. this dac selects the offset level on a linear scale between 2 reference voltages. these reference voltages are applied to vlow_dac and vhigh_dac. this offset level is adjusted dur ing the calibration phase. during this phase, the amplifier input should be constant and refers to the 'zero' signal situation. the ibis4-1300 outputs a dark reference signal after a row has been read out completely. this signal can be used as the 'zero signal' reference. alternatively one can apply an external reference on pin extin, which is applied to the output amplifier when sel_extin is 1. offset adjustment can be done during row or frame blanking time. calib_f a 1 + sel_extin extin pixel array gain [0..3] unity gain offset [0..3] d a c vhigh_dac vlow_dac calib_s clip 1.1.1.1.1 [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 11 of 35 figure 7. offset adjustment: fast offset adjustment mode there are 2 modes of offset cali bration for the output amplifier: slow and fast adjustment. figure 7. shows the timing and signal waveforms for fast offset adjust ment mode. closing both 'calib_f' and 'unitygain' operates it. after 'calib_f' is opened again, the offset level is adjusted to the de sired value in a single cycle. the signal applied to the output amplif ier should be stable just before and during the adjustment phase. the same is true for the dac output. the signal applied to the output amplifier can be either: the signal generated by the electrical dark reference in the imager core itself, i.e., the pixels named "dark" in figure 20. apply the reference from outside on the pin extin, controlled by sel_extin. if this fast offset adjustment is used, it should be done once each frame, before the readout of the frame starts, e.g., during the blanking time of the first line. figure 8. slow offset adjustment mode figure 8. shows the timing and signal waveforms for slow offset adjustment mode. it is operat ed by pulsing 'calib_s'. the amplifier input signal must be stable and refer to 'dark' signal at the moment when calib_s goes low. the offset is slowly adjusted with a time constant of about 1 00 of these pulses. one pulse is then generated during each row blanking time. the baseline is to use the fast calibration once per image. the slow calibration is intended as alternative if, for very slow readout, the offset drifts during the image. calib_f min. 500 ns stable input dark signal unitygain >0 > 100 ns calib_s min. 100 ns stable input dark signal min 100 ns [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 12 of 35 table 4. pins involved in output amplifier circuitry name no. function analog signals extin 12 external input of the output amplifier active if sel_extin = 1 output 13 analog output signal to be connected to the input of the adc (in_adc, pin 73) digital controls sel_extin 9 1 = external input pin (extin) is applied at the input of the amplifier 0 = output amplifier is connected to the image sensor array gc_bit0 17 lsb control bits for output amplifier gain setting gain adjustment between 1.2 (0000) & 16x (1111) msb gc_bit1 18 gc_bit2 19 gc_bit3 20 unitygain 21 1 = output amplifier in unity feedback mode 0 = output amplifier gain controlled by gc_bit0...3 calib_s 16 slow (or incremental) output offset level adjustment (calibration of output amplifier). offset adjustment converges after about 100 pulses on calib_s amplifier input should refer to a 'zero signal' at the moment of the 1->0 transition on calib_s 0 = connect to capacitor (of stage 2) and in- (of stage 1) 1 = connect to dac output (of stage 2) and out (of stage1) calib_f 22 fast (=in 1 cycle) output offset leve l adjustment (calibrati on of output amplifier) offset level is adjusted when bot h calib_f and unitygain are high amplifier input should refer to 'zero signal' when calib_f is high 1 = connect dac output to offset of capacitor 0 = dac output disconnected dac_b0 26 lsb control bits for output offset level adjustment between vlow_dac (0000) & vhigh_dac (1111) msb dac_b1 25 dac_b2 24 dac_b3 23 reference voltages vlow_dac 14 low and high references for offs et control dac of the analog output. the range of this resistive division dac should be about 1v to 2.5v. if the range is not ok, one will notice that it is not possible to adjust the output voltage to the appropriate level of the adc. as the internal division resistor is about 1.3 kohm, we suggest to tie vlow_dac with 1k to gnd and vhigh_dac with 2k7 to vdd. vhigh_dac 15 nbias_oamp 27 output amplifier speed/power. connect with 100 k to vdd and decouple with 100 nf to gnd. this setting yields 10 mhz nominal pixel rate. lowering the resistance does increasing this rate. clip 83 voltage that can be used to clip the output signal clips output if output signal > 'vc lip - vth, pmos' with vth,pmos=-1v default: 5 v (no clipping) [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 13 of 35 output amplifier gain control figure 9. output amplifier dc gain the output amplifier gain is controlled by a 4-bit word. in principle, the output amplifier can be configured in unity feedback mode by a permanent high signal on unitygain, but the purpose of this mode is purely diagnostic. the "normal" gain settings vary on an exponential scale. figure 9. and table 5. report all gain settings. in first approximation, the gain setting is independent of bandwidth, as the amplifier is a 2-stage design. the first stage sets the gain, and the second stage is a unity gain buffer, that determines bandwidth and slew rate. there is however some influence of gain setting on bandwidth. figure 10. shows the output amplifier bandwidth for all gain settings. 0,00 2,00 4,00 6,00 8,00 10,00 12,00 14,00 16,00 18,00 20,00 12345678910111213141516 gain setting dc gain (< 1mhz) y=1.074*2 0.246*x table 5. dc gain of output amplifier for different gain settings gain setting dc gain (<1 mhz) gain setting dc gain (<1 mhz) 0000 1.28 1000 5.33 0001 1.51 1001 6.37 0010 1.82 1010 7.41 0011 2.13 1011 8.91 0100 2.60 1100 10.70 0101 3.11 1101 12.65 0110 3.71 1110 15.01 0111 4.40 1111 17.53 [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 14 of 35 figure 10. output amplifier bandwidth for different gain settings figure 11. typical transfer characteristic of output amplifier (no clipping, voffset = 2 v, input signal during offset adjustment is 1.2 v) 0 5 10 15 20 25 30 35 unity 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gain setting bandwidth [mhz] 0 1 2 3 4 5 6 012345 input [v] output [v] unity 3 7 11 [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 15 of 35 figure 11. shows the output characterist ic curve in a typical case for the imager. the offset voltage is adjusted to 2 v, which corre- sponds to the low-level voltage of the adc. clipping is off, and the input signal is changed between 0 and 5 v. during offset adjustment (when calib_s is swit ched from 1 -> 0 or when calib_f is on), the input signal is at 1.2 v. this level corresponds to the imager dark reference output. the input signal is transferred to the output by adding a 2v offset and multiplication with the appropriate gain. the input signal of dark pixels (at 1.2 v) corre- sponds with 2 v at the output. hi gher input signals are amplified. the curves for 3 typical gain settings are shown (unity gain, setting 3, 7, and11). again, as can be seen on the above figure, the applied input signal during the output amplifie r calibration (by 'calib_s' or 'calib_f') is the reference level to which the signal is amplified. during this calibration, a stable input is required. setting of the vlow_dac and vhigh_dac reference voltages figure 12. suggested circuit for high and low references of dac vlow_dac & vhigh_dac are the reference voltages for the dac. they represent the 0000 resp. 1111 code. the internal series resistance is about 1.3 kohms. they can be connected as in figure 12. , and decoupled to ground. analog-to-digital converter the ibis4-1300 has a 10-bit flash analog-to-digital converter runni ng nominally at 10 msamples/s. th e adc is electrically separ ated from the image sensor. the input of the adc ("in_adc") should be tied externally to the output of the output amplifier. table 6. adc specifications input range 2 to 4v quantization 10 bits nominal data rate 10 msamples/s 4 dnl (linear conversion mode) inl (linear conversion mode) input capacitance < 20 pf power dissipation at 10 mhz 107 ma, 535 mw delay of digital circuitry (td, 40 pf load) < 50 ns after falling edge of clock input setup time (ts) for a stable lsb < 100 ns before falling edge of clock conversion law linear / gamma-corrected vlow_dac about 1 v vhigh_dac about 2.3 v on-chip resistor 1k3 note 4. project partners have demonstrated 20 mhz data rate by careful timing and by decreasing some or all of the resistors on nbias * and pbias*. [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 16 of 35 adc timing the adc converts on the falling edge of the clk_adc clock. the input signal should be stable during a time ts before the falling clock edge. the digital output is available td after the falling clock edge (figure 13., ts = 100 ns, td = 50 ns). these values are the delays to obtain a stable lsb after a half-scale swing of the input signal. for the msb to become stable, ts=20 ns is sufficient. for a full scale input swing (which normally doesn't appear with image sensors), ts is 140 ns for the lsb and 20 ns for the msb. figure 13. adc timing tri_adc can be used to put the output bits in a tristate mode (e.g., for bidirectional buses). if this is used, the output signal becomes valid 50 ns after the falling edge on tri_adc. bitinvert can be used to invert the output word, if necessary (one's complement). when nonlinear is high, the adc conversion is non-linear. the contrast will be higher in dark image regions, and lower in bright areas, similar to gamma correction. ts td 100 ns clk_adc in_adc d0d9 table 7. adc pins name no. description analog signals in_adc 73 input, connect to sensor's output (pin 13) input range is between 2 & 4 v (vlow_adc & vhigh_adc) digital controls clk_adc 62 adc clock adc converts on falling edge tri_adc 63 tristate control of adc digital outputs 1 = tristate; 0 = output nonlinear 67 1 = non-linear analog-digital conversion 0 = linear analog-digital conversion bitinvert 39 1 = invert output bits 0 = no inversion of output bits digital output do? d9 51?42 output bits d0 = lsb, d9 = msb [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 17 of 35 control of the vlow_adc & vhigh_adc reference voltages vlow_adc and vhigh_adc are the reference voltages for a 0 and 1023 code. a 2k-resistor ladder in ternally connects them. the appropriate 2v and 4v dc voltages can be obtained as in table 7. pins of the adc, and decoupled to ground. linear and non-linear conversion mode ? "gamma" correction figure 14. linear and non-linear adc conversion characteristic reference voltages vlow_adc 71 low reference and high reference voltages of adc should be 2v to 4v. the resistance between vlow_adc and vhigh_adc is about 1.5 k, thus this range can be approximated by tying low with 2k to gnd and high with 1k to vdd. vhigh_adc 61 pbiasdig1 64 connect with 100k to gnd and decouple to vdd pbiasencload 65 connect with 100k to gnd and decouple to vdd pbiasdig2 66 connect with 100k to gnd and decouple to vdd nbiasana2 69 connect with 100k to vdd and decouple to gnd nbiasana 70 connect with 100k to vdd and decouple to gnd these resistors determine the analog resp. digi tal speed /power of the adc. both can be increased/decreased by lowering or increasing the resistance values. power and ground vdd_dig 56, 76 power supply of digital circuits of adc, + 5 v vdd_an 58, 74 power supply of analog circuits of adc, + 5 v gnd_dig 57, 75 ground of digital adc circuits gnd_an 60, 72 ground of analog adc circuits table 7. adc pins (continued) name no. description 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 2.0 2.5 3.0 3.5 4.0 input signal [v] output linear non-linear [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 18 of 35 figure 14. shows the adc transfer characteristic. for this measuremen t, the adc input was connected to a 16-bit dac. the input voltage was a 100 khz triangle waveform. the non-linear adc conversion is intended fo r gamma-correction of the images. it incr eases contrast in dark areas and reduces contrast in bright areas. the non-linear curve is tolerant for external pixel offset error corre ction. this means that pixel of fset variations can be corrected by changing the offset after the non-linear ad c onversion. this is so because the non-linear transfer function is h(s) = 1-exp(-a*s) by design, and neglecting the offset, the relation between t he non-linear output (y) and the li near output (x) is exactly: y = 1024 * (1 - exp(-x/713)) / (1 - exp(-1024/713)) this law yields an increased accuracy of ab out a factor 2 near the zero end of the scale. it is thus possible to obtain an effe ctive 11 bit accuracy on a linear scale after post processing by applying the reverse law to the non-linear output: z = -2 * 713 * ln(1 - y/(1024/(1-exp(-1024/713)))) = -1426 * ln(1-y/1343.5) then z is an 11-bit linear output in the range 0...2047. [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 19 of 35 operation of the image sensor set configuration and pulse timing figure 15. typical operation mode (readout of a frame) figure 15. shows a typical operation mode of the image sensor. at the start of a new frame, the device may be reconfigured. if necessary, the output amplifier gain and offset are adjusted or the device is put in viewfinder mode. then, the frame readout shift r egister is initiated by pulsing "sync_yr". this pulse occurs once per frame, normally as a part of the first row blanking sequence. the readout of a row (line) starts with row blanking initialization sequence. here several pulses are applied for y-direction shift, the column amplifier s&h and nulling, and the start (sync_x) of the x-direction shift register. the frame reset shift register is started also once per frame by "sync_yl", this pulse occurs once per frame, normally as a part of the row blanking sequence of one particular row. the time delay from the sync_yl to sync_ yr is the integration time. the integration is thus a multiple of the row readout time. the reset shift register always le ads the readout shift register. therefore, the integration time should be determined before the start of the frame readout. the valu e that is fixed at that moment will be the integration time of the next frame. if the value set for the integration time changes dur ing frame readout, the start pulse might be lost and the next frame might be invalid. we will now discuss all steps in more detail. set configuration - output offset -amplifiergain - viewfinder on/off - determine integration time of next frame set flag to restart yr shift register with sync_yr execute row initialization sequence a cquire pixel (x,y) for y = 0 till ymax do y= 1026 - integration time ? for x = 0 to xmax do setflagtorestartylshift register with sync_yl no x yes startxshiftregister sync_x next y [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 20 of 35 set configuration configuration of the image sensor implies control and adjustment of the following points: output amplifier offset level, set by 'dac_bit[0...3]' output amplifier gain setting, set by 'gc_bit[0...3]' choose the integration time of the next frame set/clear viewfinder mode (pin 'subsampl') in case when the fast adjustment of the offset level is used, plus 'calib_f' and 'unitygain' as described before in figure 7. and figure 8. viewfinder mode versus normal readout in full image readout mode (pin 84, subsmpl = 0), the imager is a 1280 x 1024 sxga image sensor. there are 3 dummy pixels read at all 4 borders of the image. in viewfinder mode (subsmpl = 1), the imager acts as a 320 x 256 qvga image sensor with one du mmy pixel at the start of a row/column. table 8. shows which column or row is selected after a number of clock pulses. start of the y shift registers for row readout and row reset the shift registers are put in their initial state by a synchronization- or start pulse. (sync_x, sync_yr, sync_yl). the synchronization signal is low-active and should only be generated when the clock of the shift register is high. after the synchronization pulse, two falling clock edges are needed to skip dummy pixels/lines. on every falling clock edge, the shift register selects a new row for readout or reset. figure 16. shows this timing. table 8. coordinate of row or column selected by y/x shift re gisters after a # clock periods in viewfinder mode and full image mode clock sync 1 2 3 4 5 6 viewfinder mode none none row 1 row 5 row 9 row 13 row 17 y reg. dark col. 1 col. 5 col. 9 col. 13 x reg. full image mode none none row 1 row 2 row 3 row 4 row 5 y reg. dark col. 1 col. 2 col. 3 col. 4 x reg. clock 258 259 260 322 323 324 viewfinder mode row 1025 row 1029 eos col. 1281 col. 1285 eos dark clock 1030 1031 1032 1287 1288 1289 full image mode row 1029 row 1030 eos col. 1285 col. 1286 eos dark y shift register x shift register [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 21 of 35 figure 16. timing of y shift registers (for row selection) figure 17. end-of-scan pulse end-of-scan: eos_yl, eos_yr, eos_x all three shift registers are equipped with 'end-of-scan' pulses. these pulses are low during the clock period after the last pixel or row has been read out, also in viewfinder mode. at the eos_x pulse, the electrical dark reference level is put on the readout bus. this voltage re mains on the bus until the sin pulse goes high. during the row blanking time, this voltage can be used for the offset adjustment of the output amplifier. the sin high forces the dcref voltage on the output bus. we advise not to use the eos pulses as an input for the row blanking time sequence generation, but to use simple counters instead. if by some reasons the eo s signal is absent or subject to glitches, the system would hang. eos is intended as diagnostic means. row initialization during the row blanking time (which occurs at the beginning of every row read), several tasks ar e executed: selection of a new row, readout of this row by double sampling, reset of a new row, and possibly (slow) offset adjus tment of the output amplifier. therefore, a pulse patterns must be applied to several signals during this time. there is some fr eedom to make this pattern. the constraints are listed below: syncy clck_y min 100 ns. min 25 ns 1 2 3 4 5 0 nil n n- dummy rows 1 line selected 0 col 1286 row 1030 col 321 row 257 clock eos [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 22 of 35 figure 18. timing constraints for ro w readout initialization (blanking time) sync_yl sync_y r clk_yr clk yl tc sh y sin reset l/r sync_ x ts tr tr tw th to to to tm tn clock_ x table 9. timing constraints on row initialization pulses sequence ta min 0 delay between falling edge of clk_y* and shy or sin tc min 25 ns clk_yr & clk_yl high time ts typ. 3 s on-time of sin (offset calibration pulse) delay between selection of new row and end of column amplifier calibration tw typ. 200 ns delay between end sin and pixel reset tr typ. 1 s on-time of reset pulse th typ 1 s th + tr = delay between pixel reset and column sample & hold to typ 100 ns delay between shy and l/r\ overlap of l/r\ over 2nd reset pulse tm min 25 ns on-time of one of the sync pulses. sync==low may only occur when the associated clock is high. tn min. 200 ns delay between shy and start row readout [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 23 of 35 figure 18. and table 9. illustrate the timing constraints of the row initialization/ blanking sequence. the eos_x pulse flags the end of the scanning of previous line, and should be considered as a diagnostic means only. the blanking sequence could start earlier or later. the next row (=line) is selected after the falling edge of clk_yr and clk_yl, the column amplifiers receive the signals on the pixels array columns buses when shy is low (transparent). the sin pulse (high) forces the column amplifiers in an ?offset nulling" state. after 3 us, the column amplifiers have reached offset-free equilibrium, and the sin pulse is brought low again. the pixel's signal level is thus stored in the column amplifier. after that the pixels in the selected row (line) are be reset (first pulse on reset). consequently the reset level is frozen in the column amplifiers when shy goes high. both signal level and reset level have now been applied to the column amplifiers. the sample hold (shy) guarantees that this information will not change anymore during readout of the line. now, the row is ready for readout. a pulse on sync_x must be given to start the row readout. sync_x initiates the x-direction scanning register. the scanning itself is controlled by clock_x. during the beginning of the row readout, or possibly before, the reset pulse for the electronic sh utter (es) must be given, if the es is used. this is a pulse on reset together with a high level on l/r. if the es is not used, l/r remains low and the second reset pulse is not generated. during some or the entire row blanking times, the output amplifier can be calibrated. if the slow calibration method is used, pulse the 'calib_s' pin once per line. the calibration happens on the rising edge of the pulse. if the fast calibration is used, the 'calib_f' should be pulsed during the row blanking time of the first row only. this calibration happens during the time that the pulse is high. during this calibration, the input applied to the amplifier must be the dark reference, which can eith er be the built-in electrical dark reference, or an external dark reference on the pin extin. figure 19. pulse on 'calib_f'& 'unitygain' to be given once per frame, or on calib_s once per line the x-direction shift register the x shift register behaves like the y shift registers. the sequence if initiated by sync_x, which should occur when clock_x is high. as clock_x is halted during the blanking time, the sync_x pulse could occur anywhere, and be taken equal to some other pulse (e.g. clock_y). the first real (dummy) pixel is read out after the 3rd falling edge on the clock. dummy pixels are perfectly operational pixels, but are added to shield the "real" pixels from the cross talk of the periphery. signal applied to input of amplifier calib_s or calib_f 500ns (calib_f) "dark" reference 100ns 100ns (calib_s) [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 24 of 35 figure 20. timing of x shift register and pixels readout on-chip generated electrical dark references the sensor outputs a electrical dark reference level after the 2nd falling edge on the clock (after sync). at the end of the row readout, after eos_x becomes low, the sensor outputs the electrical dark reference voltage also, and it remains present on the on the readout bus until sin goes high. note that if the x-register is re set before the eos is reached, the dark reference is not put on the bus. use the dark reference of the beginning of the line instead. pixel readout the same continuous 10 mhz clock drives clk_adc and clk_x. on the falling edge of clk_x, a new pixel is selected and propagates to t he output amplifier. at the same time, the adc input is frozen by the falling edge on clk_adc. the digital output has a delay of one pixel compared to the analog signal. the digital output becomes valid between 25 to 50 ns after the falling edge on clk_adc. figure 21. pixel timing if the end of a row is reached, the sensor outputs an end-of-scan (eos) pulse during one pulse period. and the electrical black reference level appears at the output for all successive pulses. so, the same 10 mhz clock can drive clk_x and clk_adc. dcref on bus sync clock min 100 ns. min 25 ns 0 1 2 3 4 dark nil n n-1 dummy pixels 1 outpu t 0 tp,adc [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 25 of 35 example: timing used on ibis4 breadboard the next figure is the timing as used in the ibis4 breadboard version 12 january 2000. in this baseline only calib_f is used (pulsing once per frame). calib_s (pulse every line) is shown as reference, but is actually not used in the baseline. the unity_gain pulse is identical to calib_f. figure 22. pulse sequence used in ibis4 breadboard v. january 2000 illumination control there are two means of controlli ng the illumination level electri- cally. for high light levels, there is an electronic shutter. for low light levels, the output signal can be amplified by controlling the output amplifier gain. the offset level of the signal can also be controlled digitally. ?rolling curtain" electronic shutter the electronic shutter can reduce the integration time (= exposure time). this is achieved by an additional reset pulse every frame. in this way, the in tegration time is reduced to a fraction of the frame readout time. there are two y shift registers. on e of them points at the row that is currently being read out. the other shift register points at the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between both pointers. figure 23. schematic representation of curtain type elec- tronic shutter this is a so-called 'rolling curtain'-type shutter. it 'rolls' over the focal plane. the left and right shift registers can be used both for pointing to the row that is readout or the row that is reset. the shift register that is active for readout or rese t is selected by the signal on l/r. in the above timing diagrams, we use the r shift register for readout, and the l shift register for electronic shutter reset. we call them the readout shift register and reset shift register. the integration time is controlled by the delay between the syncy_l and syncy_r pulse. the shorter this delay, the shorter the integration time and the smaller the output signal will be. if the electronic shutter is not us ed, the l/r signal is not pulsed. the integration time is then equal to the frame readout time. for proper operation of the es, the clock_y must come as an uninterrupted pulse train. also during the dead time between frames the clock_y must be clocked. the reason is that each line should see the same elapsed time between the "es-reset" and the reset of the line being read-out. if the clock_y is halted, the lines between the tw o pointers will have a longer effective integration time, and appear brighter. gain control for low illumination levels, the electronic shutter is not used - or set to its maximal value. longer integration times can only be obtained by decreasing the fram e rate. as an alternative or in complement, one can increase the output amplifier gain. the gain is controlled by a 4-bit word. gain values vary between 1.2 and 16, and on an exponential scale, as the f-stops of a lens. of course, increasing the signal amplitude by increasing the gain, will also increase the nois e level. the apparent increase of sensitivity is at the cost of a lower dynamic range. clck_y sin calib_s or calib_f&unity gain reset sync_x clck_x syncy_l and syncy_r; once per frame per register (for electronic shutter l and r at different moments) l/r shy 1usec is calib_s is used, calib_f&unity are 0 is calib_f&unity are used, calib_s is 0 integration time readou t pointe r reset pointer [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 26 of 35 offset level adjustment the offset level of the output signal is set by a 4-bit digital word. the offset level voltage is selected between vlow_dac and vhigh_dac on 16 taps. "double slope" or "high-dynamic range" mode ibis4-1300 has a feature to incr ease the dynamic range. the pixel response can be extended over a larger range of light inten- sities by using a "dual slope integration" (patents pending). this is obtained by the addition of charge packets from a long and a short integration time in the pixel during the same frame time. figure 24. response curve of the pixels in dual slope integration figure 24 shows the response curve of a pixel in dual slope integration mode. the curve also shows the response of the same pixel in linear integration mode, with a long and short integration time, at the same light levels. dual slope integration is obtained by feeding a lower supply voltage to vdd_resetl, e.g., apply 4 to 4.5 volts. the difference between this voltage and vdd determines the range of the high sensitivity, thus the output signal level at which the trans ition between high and low sensi- tivity occurs. put the amplifier gain to the lowest value where the analog output swing covers the adc's di gital input swing. increasing the amplification too much will likely boost the high sensitivity part over the whole adc range. the electronic shutter determines the ratio of integration times of the two slopes. the high sensitivity ramp corresponds to "no electronic shutter", thus maximal integration time. the low sensitivity ramp corresponds to the electronics shutter value that would have been obtained in normal operation. these example images are found at http://www.fillfactory.com/htm/ technology/htm/dual-slope.htm . figure 25. linear long exposure time 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0% 20% 40% 60% 80% 100% relative exposure (arbitrary scale) output signal [v] dual slope operation long integration time short integration time [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 27 of 35 figure 26. linear short exposure time figure 27. double slope integration electrical parameters dc voltages vdd and gnd nominal vdd-gnd is 5v dc. overall current consumption for the different parts. imager core + output amplifier analog imager core digital adc analog adc digital are quoted in the data sheets. the sensor works properly when using a 7805 type of regulator. decoupling vdd to gnd must happen close to the ic. other applied dc voltages should be clean as the vdd. can be derived by resistive division of vdd-gnd, and decoupled to vdd or gnd (as indicated) external resistors are used as current mirror settings. should be decoupled to the opposite rail voltage as the connectio n of the resistor (thus: if the resistor is tied to vdd, the capa citor is tied to gnd). in practice the decoupling can be omitted for almost all signals - to be experimented. input / output digital inputs clean rail to rail cmos levels. 10%-90% rise and fall times between 10 ns and 40 ns digital outputs deliver cmos level, able to drive 40 pf capacitive loads analog output of imager core designed to drive a 40 pf capacitive load analog input of adc is equivalent to a capacitive load of typ. 15 pf [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 28 of 35 pin configuration pin list signal type symbols a analog d digital w word bit i/o symbols i input o output p power supply g ground no. name type i/o description signal 1 nbiasarray a i 1meg to vdd and decouple to gnd pixel source follower bias current 2 pbias2 a i 1meg to gnd and decouple to vdd column amp 1st source follower (after shy) bias current 3 pbias a i 1meg to gnd and decouple to vdd c olumn amp current source bias current 4 xmux_nbias a i 100k to vdd and decouple to gnd x-multiplexing bias current (/6) 5 sync_yr\ d i low active (0=sync) 0 = reset right shift register 6 clk_yr d i shifts on falling edge clock right shift register 7 eos_yr\ d o active low low 1st clk_yr pulse after last row 8 eos_x\ d o active low low 1st clk_x pulse after last active column 9 selextin d i input selector for output amplif ier 1 = external input; [0] = imager core 10 gnd a g analog gnd 11 vdd a p analog vdd + 5 v dc 12 extin a i external input to output amplifier 13 output a o analog output of imager core connect to in_adc (p73) 14 vlow_dac a i low reference voltage offset dac +/- 1 v 15 vhigh_dac a i high reference voltage offset dac +/- 2.5 v 16 calib_s d i slow dark offset level adjustment 0: connect to cap (st2) and in- (st1) 1: connect to rdac (st2) and output (st1) 17 gc_bit0 w i lsb gain control output amplifier 18 gc_bit1 w i 19 gc_bit2 w i 20 gc_bit3 w i msb 21 unitygain d i sets output amplifier in unity gain high active 22 calib_f d i fast dark offset level calibration high active 23 dac_b3 w i msb dac control for black offset level 24 dac_b2 w i dac control for black offset level 25 dac_b1 w i dac control for black offset level 26 dac_b0 w i lsb dac control for black offset level 27 nbias_oamp a i 100k to vdd and decouple to gnd output amplifier bias current 28 sync_x\ d i low active (0=sync) 0 = reset x shift register [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 29 of 35 29 clk_x d i shifts on falling edge clock x shift register 30 shy d i column parallel track and hold 1 = hold; 0 = track 31 dccon a i control voltage for dc reference gener- ation connect to gnd (default) 32 dcref a o reference voltage should be +/- 1.2 v, depends on dccon 33 gnd a g 34 vdd a p 35 sin d i column amplifier calibration signal 1 = calibrate, see timing diagram 36 sync_y\l d i 0 = start left shif t register low active (0=sync) 37 clk_yl d i clock left shift register shifts on falling edge 38 eos_yl\ d o low 1st clk_yl pu lse after last row active low 39 bitinvert d i high active, 1 = invert bits inverts adc output bits 40 select d i high active selects row indicated by left/right shift register 41 reset d i high active resets row indicated by left/right shift register 42 d9 w o msb adc output 43 d8 w o 44 d7 w o 45 d6 w o 46 d5 w o 47 d4 w o 48 d3 w o 49 d2 w o 50 d1 w o 51 d0 w o lsb 52 gnd a g 53 vdd a p + 5 v dc 54 gnd_ab a g anti-blooming drain voltage gnd or +1v for improved anti-blooming 55 vdd_array a p + 5 v dc pixel power supply 56 vdd_dig d p + 5 v dc adc digital power supply 57 gnd_dig d g adc ground of digital circuits 58 vdd_an a p + 5 v dc adc analog power supply 59 vdd_resetl a p 5 v dc default (5.5 v for large output swing) 4?4.5 v for double slope mode vdd for reset by left shift register 60 gnd_an a g adc ground of analog circuits 61 vhigh_adc a i + 4 v dc high adc reference voltage 62 clk_adc d i adc clock converts on falling edge no. name type i/o description signal [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 30 of 35 bonding pad geometry for the ibis4-1300 the 84 pins are distributed evenly around the perimeter of the chip. at each edge there are 21 pins . pin 1 is (in this drawing) in the middle of the left edge. the opening in the bonding pads (the useful area for bonding) is 200 x 150 um. the centers of the bonding pads are at all four edges at 150 um distance from the nominal chip border. the scribe line (=the spacing between the nominal borders of neighboring chips) is 250 um. the bonding pad pitch is 437 um in x-direction. the bonding pad pitch in y-direction is 393 um. 63 tri_adc d i adc output tristate control 1=tristate; 0=output 64 pbiasdig1 a i 100k to gnd and decouple to vd d current bias for comparator after encoder 65 pbiasencload a i 100k to gnd and decouple to vdd current bias for encoder 66 pbiasdig2 a i 100k to gnd and decouple to vdd current bias for digital logic in columns 67 nonlinear d i high active (1 = non-linear conversion) control for non-linear behavior of sensor 68 n.c. not connected 69 nbiasana2 a i 100k to vdd and decouple to gnd bias current 2nd comparator stage 70 nbiasana a i 100k to vdd and decouple to gnd bias current 1st comparator stage 71 vlow_adc a i + 2 v dc, +-2 k between p71 and p61 low adc reference voltage 72 gnd_an a g adc ground of analog circuits 73 in_adc a i converts between vlow and vhigh (2-4v) adc input 74 vdd_an a p + 5 v dc adc analog power supply 75 gnd_dig d g adc ground of digital circuits 76 vdd_dig d p + 5 v dc adc digital power supply 77 vdd a p + 5 v dc 78 gnd a g 79 vdd_resetr a p 5 v dc default (5.5 for large signal swing) power supply for reset by right (readout) shift register 80 l/r\ d i 1=left; 0=right selects left or right shift register for 'select' and 'reset' 81 pixel diode a o groups current of 24 x 18 pixels test structure for spectral response measurement of pixels 82 photodiode a o 168x126 um2 (eq. 24 x 18 pi xels) test structure for spectral response measurement of photodiode 83 clip a i clips if output > 'clip' - vth (pmos) clipping voltage for output amplifier 84 subsmpl d i high active, 1 = subsampling selects viewfinder mode (1:4 = 320 x 256) no. name type i/o description signal [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 31 of 35 relative position of pads in corners: see the following figure (measures in um). color filter geometry sensors with diagonal pattern have: pixel (1,1) is red first line sequence is b g r b g r second line sequence is r b g r b g b sensors with bayer pattern have: pixel (1,1) is green first line sequence is g r g r g second line sequence is b g b g b 393 468 437 627 474 635 10158 9265 150 [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 32 of 35 package 84 pins ceramic lcc package (jlcc also available) standard 0.04 inch pitch outline 0.46" square cavity die thickness nominally 711 um +- 50um clearance from top of die to bottom of glass lid: 400um nominally figure 28. pin layout and package, top view cover glass size 18x18 mm for jlcc and lcc color sensor refractive index: 1,55 thickness: 0,75+-0.05 mm material: bg39 this material acts a nir cut-off filter. the transmission characteristics are given in the figures ahead. the data used to create the transmission curve of the bg39 material can be obtained as an excel file upon simple request to info@fillfactory.com. 54 74 12 32 84 diagonal stripe pattern image sensor core adc pin1 11 33 53 75 0,0 1280,1024 568 m 1169 m 885 m 588 m [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 33 of 35 figure 29. transmission characteristi cs of bg39 glass used as nir cut-off filter for ibis4-1300 color image sensors monochrome sensor refractive index: 1,52 thickness: 0,55+-0.05 mm material: d263 the transmission characteristics are given in figure 30 below. figure 30. transmission charac teristics of d263 glass used as protective cover for ibis4-1300 monochrome image sensors bg39 transmission characteristics 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 400 500 600 700 800 900 1000 wavelength transmission d263 transmission characteristics 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 400 500 600 700 800 900 wavelength transmission [+] feedback
cyii4sm1300aa document number: 38-05707 rev. *c page 34 of 35 ordering information faq temperature dependence of dark signal the above graph is measured on an ibis4-1300 under nominal operation, using breadboard. this particular sensor has about 100 "bad pixels" at rt. average offset (=dark signal) and rms (=fpn of dark signal) are measured versus temperature. offset is referred to the "short tint" offset at 20 c. integration time was 160 ms (= "long tint"). y-axis is the output signal (100% = adc range) useful range of "double slope" which total dynamic range can reasonably be obtained with the dual slope feature of the ibis4-1300? assuming that the "regular" s/n is 2000:1, and that one can put the knee point halfway the voltage range, the each piecewise linear halve has 1000:1 s/n. if the ratio between slopes is a, then the total dynamic range becomes (1000+a*1000):1. example, is a=10, then the total dynamic range becomes 11000:1. in practice, acceptable images are obtained with a up to 10. larger a's are useable, but near the knee, contrast artifacts become annoying. skipping rows or columns although these modes are not described in the datasheets, it is possible to skip rows or columns by simply applying additional clk_yr + clr_yl, or clk_x pulses. the maximum clock frequency is not documented. but it is probable that one can reach at least 10 mhz in y and 40 mhz in x. disclaimer fillfactory image sensors are only warranted to meet the speci- fications as described in the production data sheet. specifica- tions are subject to change without notice. marketing part number description package CYII4SM1300AA-QDC mono with glass 84-pin lcc cyii4sm1300aa-qwc mono without glass cyii4sd1300aa-qdc color diagonal with glass ibis 4c 0,1 1 10 100 1000 20 30 40 50 60 70 80 90 offset long tint rms long tint #pixels outside 6sigma nominal operation, 512 x 512 pixels corner, 160 ms tint % of saturation [+] feedback
document number: 38-05707 rev. *c revised september 21, 2009 page 35 of 35 purchase of i2c components from cypress or one of its sublic ensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defi ned by philips. as from october 1st, 2006 philips semiconduct ors has a new trade name - nxp semiconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cyii4sm1300aa ? cypress semiconductor corporation, 2006-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cyii4sm1300aa ibis4-1300 1. 3 mpxl rolling shutter cmos image sensor document number: 38-05707 rev. ecn issue date orig. of change description of change ** 310213 see ecn sil initial cypress release. *a 509557 see ecn qgs converted to frame file. *b 642577 see ecn fpw ordering information update. *c 2766920 09/21/2009 nvea update ordering information and template. add part number to title. [+] feedback

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